AUTOMATA: SERCON100 FPGA reference design

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SERCOS III • SERCON100 FPGA • IP cores & FPGA types




		SERCON100 reference implementation

SERCON100 IP cores and supported FPGA types

For SERCOS III implementation three different FPGA IP cores are available:

SERCON100M: SERCOS III master

SERCON100S: SERCOS III slave with 32bit data- and 16bit address bus

SERCON100SL: SERCOS III slave with 16bit data- and 12bit address bus

For hardware designs in accordance with the reference implementation IP cores in bitstream format are used. The netlist format is used if the hardware design is not compliant to the reference design or additional functions in the FPGA shall be integrated.

To get data sheets or other additional informations regarding the SERCOS III IP cores use the contact form or visit the homepage of SERCOS International.

supported FPGA manufacturers and types

Master SERCON100M	Bitstream	Cyclone II: EP2C35 Cyclone III: EP3C10	Spartan 3: XC3S400BGA256
Master SERCON100M	Netzliste	Cyclone II/III (check data sheet for resources, global clocks etc.)	Spartan 3: (check data sheet for resources, global clocks etc.)
Slave SERCON100S SERCON100SL	Bitstream	Cyclone II: EP2C20 Cyclone III: EP3C10	Spartan 3: XC3S400BGA256, XC3S400TQFP144 (only SERCON100SL)
Slave SERCON100S SERCON100SL	Netzliste	Cyclone II/III (check data sheet for resources, global clocks etc.)	Spartan 3: (check data sheet for resources, global clocks etc.)