For SERCOS III implementation three different FPGA IP cores are available:

 

SERCON100SL: SERCOS III slave with 16bit data- and 12bit address bus

 

For hardware designs in accordance with the reference implementation IP cores in bitstream format are used. The netlist format is used if the hardware design is not compliant to the reference design or additional functions in the FPGA shall be integrated.

 

To get data sheets or other additional informations regarding the SERCOS III IP cores use the contact form or visit the homepage of SERCOS International.